Digital Ultra Low Voltage High Speed Logic

Low power is becoming more and more crucial and in many aspects becoming the number 1 priority when designing new applications. Ultra low voltage CMOS is an approach for producing very low-power CMOS circuits by reducing the supply voltage to several hundred millivolts [1, 2]. To maintain good performance at low supply voltages, the threshold voltages of MOS transistors must also be reduced [3–5]. Unfortunately, this requires a change in the CMOS fabrication process. Because variations in Vth, when operating in a low-Vdd and low-Vth environment, cause significant variations in performance, the ultra low power approach lies on the biasing of transistor bodies to adjust thresholds [3]. The primary drawbacks to ultra low power CMOS are that it requires (i) a change in the fabrication process, (ii) additional circuitry to adjust body potential, and (iii) additional routing of separate well-voltage (Vp-well and Vn-well) references.